Delay locked loops (DLLs) are widely employed for clock generation and synchronization as an alternative to other forms of timing generators, such as phase locked loops (PLLs). A DLL permits the significant timing edges of the timing signal to be phase shifted. DLLs generally comprise a delay line having tunable delay elements for delaying a reference timing signal, and a phase detector that determines the phase difference between the reference timing signal and the delayed reference signal. A control circuit is then used to convert this phase difference into appropriate control signals for tuning the delay line.
DLLs provide the advantage with respect to PLLs of better jitter performance, because phase errors are not accumulated in noisy environments.
It has been proposed to provide fully digital DLLs, which provide the advantage of benefiting from CMOS technology scaling, allowing reduced chip area, reduced power consumption, and ease of migration towards future advanced CMOS process nodes. However, fully digital DLLs generally lead to high design complexity, and thus a relatively high circuit area and power consumption.
There is thus a need in the art for a fully digital DLL providing relatively low complexity, low surface area and low power consumption.